The reduction in memory cell sizes required for high density dynamic random access memories (DRAMs) results in a corresponding decrease in the area available for the storage node of the memory cell capacitor. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area. Several techniques have been developed to increase the total charge capacity of a cell capacitor without significantly affecting the cell area. These include new structures utilizing trench and stacked capacitors, as well as the utilization of new capacitor dielectric materials having higher dielectric constants.
One common material utilized for the capacitor plates is conductively doped polysilicon. The prior art has recognized that the capacitance using such materials can be increased merely by increasing the surface roughness of the polysilicon film that is used as a storage node. Such roughness is typically transferred to the cell dielectric and polysilicon layer, resulting in a larger surface area for the same planar area that is available for the capacitor. One procedure utilized to achieve surface roughening involves deposition under conditions which are intended to inherently induce a rough or rugged upper polysilicon surface. Such techniques include low pressure chemical vapor deposition (LPCVD).
Such rugged polysilicon films additionally must be conductively doped after deposition. Such doping techniques include standard thermal phosphorus diffusion or ion implantation. These techniques require additional processing steps after rugged polysilicon film deposition. Each has also been observed to reduce the surface roughness of the film as a result of the doping, thereby reducing desired surface roughness leading to a lower gain in the capacitance per unit area.
Alternately, such polysilicon layers can be provided in two steps. A first underlying layer, perhaps deposited to a thickness of one-half the total desired layer, is deposited and heavily conductively doped with phosphorus. Thereafter, a second polysilicon film is deposited in a manner intended to induce roughness. The wafer is subsequently subjected to various processing steps which provide the added side effect of heating the wafer and causing conductivity impurity diffusion from the underlying layer to the upper layer. This alternate two-layer poly can include first depositing an undoped polysilicon layer. Thereafter, such layer is subjected to thermal phosphorus diffusion or ion implantation. In the course of such phosphorus diffusion, the wafer is typically subjected inadvertently to oxidizing conditions causing an undesired layer of oxide to be grown. Such oxide layer is typically at least 200 Angstroms thick, which is sufficient to create an effective insulating layer such that an undesired sub-capacitor would be formed within one of the storage nodes. Accordingly, the prior art completely removes this oxide layer by subjecting the wafer to a wet oxide strip, leaving an upwardly smooth polysilicon surface. With the oxide completely removed, a layer of undoped polysilicon is deposited. The wafer is subsequently subjected to heating steps which cause diffusion of conductivity enhancing impurity from the lower polysilicon layer to the upper polysilicon layer.
It would be desirable to improve upon these and other prior art techniques in developing electrically conductive polysilicon capacitor plates having enhanced capacitance for a given cell area.